Field of the Invention
The invention relates to an integrated memory with interblock redundancy.
An integrated memory with interblock redundancy is described in European Patent EP 0 636 258 B1. The memory is divided into a plurality of memory blocks that each contain bit lines and word lines as well as redundant word lines. The redundant word lines are used for replacing the normal word lines in address terms in the case of redundancy. If one of the normal word lines is defective, address replacement can be performed by carrying out redundancy programming. The redundant word lines in European Patent EP 0 636 258 B1 are not used to replace defective word lines in the same memory block (xe2x80x9cintrablock redundancyxe2x80x9d) but rather to replace word lines in any one of the memory blocks. This is referred to as xe2x80x9cinterblock redundancyxe2x80x9d. In order to avoid short-circuits between the memory cells, it is necessary to ensure that at most one word line is activated at a given time per memory block. Since, in the case of interblock redundancy, the block from which the replacing redundant word line will originate is not defined in advance, the European Patent EP 0 636 258 B1 provides that at most one of the memory blocks of the interblock redundancy area can be activated at a given time. The memory has a deactivation line via which all the memory blocks of the interblock redundancy area can be deactivated by an inhibit signal. The memory block that has been defined as the one in which one of the redundant word lines will be activated is exempted from this deactivation. This memory block generates the inhibit signal.
The prior art described has the disadvantage that in each case just one memory block can ever be activated at a given time within the interblock redundancy area.
It is accordingly an object of the invention to provide an integrated memory with interblock redundancy which overcomes the above-mentioned disadvantages of the prior art devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory. The memory contains deactivation lines and memory blocks including a first memory block and a second memory block. Each of the memory blocks contains row lines, column lines intersecting the row lines at intersection points, memory cells disposed at the intersection points of the column lines and the row lines, and at least one redundancy row line for replacing, in each case, one of the row lines in any of the memory blocks and intersecting the row lines. A deactivation unit for deactivating a respective memory block and having an input and an output is provided, the input is connected to one of the deactivation lines. A deactivation decoder is provided and has an output end connected to the deactivation lines assigned to other ones of the memory blocks. If one of the row lines of the first memory block of the memory blocks is replaced by the redundancy row line of the second memory block of the memory blocks, the deactivation decoder of the second memory block deactivates the first memory block through a corresponding one of the deactivation lines.
The integrated memory according to the invention has memory blocks with deactivation units for deactivating them. In addition, it has, for each memory block, a deactivation line which is respectively connected to an input of its deactivation unit. Each memory block has a deactivation decoder that is connected at the output end to the deactivation lines assigned to the other memory blocks. When one of the row lines of a first memory block of the memory blocks is replaced by a redundancy row line of a second memory block of the memory blocks, the deactivation decoder of the second memory block deactivates the first memory block via the corresponding deactivation line.
In the invention, when there is redundancy, only that memory block whose row line is to be respectively replaced is deactivated via the appropriate deactivation line. In contrast, in European Patent EP 0 636 258 B1, in the case of redundancy all the memory blocks are deactivated with the exception of that memory block which has the redundant row line. In European Patent EP 0 636 258 B1, the simultaneous deactivation of all the memory blocks takes place via just one common deactivation line. In the invention, a deactivation line is assigned to each memory block.
According to a first embodiment of the invention, the column lines are bit lines and the row lines are word lines. There is then interblock redundancy with respect to the word lines. According to another embodiment of the invention, the column lines are word lines and the row lines are bit lines of the memory, so that there is then interblock redundancy with respect to the bit lines.
The invention is particularly advantageous if the integrated memory contains memory blocks, of which more than one can be activated simultaneously. If, for example, in each case two of the memory blocks of the interblock redundancy area could be activated simultaneously, in the procedure according to European Patent EP 0 636 258 B1 all the other memory blocks would be deactivated by the memory block with the replacing redundant line in the case of redundancy. In contrast, according to the invention, on the basis of the redundancy activated, just that memory block whose row line is to be replaced by the redundant line is ever deactivated via its deactivation line by the corresponding memory block. Given two memory blocks that are to be activated simultaneously, the activation of the one memory block therefore remains unaffected if a row line is replaced in the other memory block by a redundant row line of a third memory block. Of course, it is also unproblematic if defective row lines in the two memory blocks which are to be activated simultaneously are to be replaced at the same time by redundant row lines in other, respectively different memory blocks of the interblock redundancy area. The memory block with the replacing redundant row line deactivates in each case the associated memory block with the normal row line which is to be replaced. The number of memory blocks that can be activated simultaneously therefore always remains constant, even in the case of redundancy.
According to one embodiment of the invention, the integrated memory has an address bus connected to the memory blocks, for transmitting block addresses and row addresses. The memory blocks each have at least one redundancy memory unit for storing the block address and the row address of one of the row lines which is to be replaced by the redundancy row line of this memory block. In addition, the memory blocks have, for each redundancy memory unit, in each case one comparator unit for comparing the address transmitted via the address bus with the address stored in the corresponding redundancy memory unit, which, given correspondence, activates a corresponding result signal at a result output. The deactivation decoders of the memory blocks have inputs that are connected to the associated redundancy memory unit for supplying the block address of the row line which is to be respectively replaced, and a further input which is connected to the result output of the comparator unit of the corresponding memory block. If the corresponding result signal is activated, the deactivation decoders deactivate via the corresponding deactivation line that memory block whose block address is supplied to them from the redundancy memory unit.
According to one development of the invention, the block addresses are encoded with n address bits. At the same time, in each case at least two of the memory blocks can be addressed using common block group addresses which are encoded with m  less than n address bits which are parts of the block addresses. The redundancy memory units in turn store the block address and the row address of the row line which is to be respectively replaced. The comparator units compare the address stored in the associated redundancy memory unit with the block group address present on the address bus and the row address. The inputs of the deactivation decoders are supplied by the redundancy memory units with the complete block address of that memory block whose row line is to be replaced.
This development of the invention is concerned with the previously described case in which more than one of the memory blocks of the interblock redundancy area can be activated simultaneously. Since the memory blocks which are to be activated simultaneously can be addressed via a common block group address, the width of the address bus is reduced, because only a relatively small number m of address bits have to be transmitted to the memory blocks instead of the n address bits of the complete block addresses. Furthermore, the comparator units can be of simpler construction because they only have to compare the relatively small number of m block group address bits. However, the deactivation decoders are supplied not only with the block group address which is transmitted via the address bus but also with the complete block address of the row line which is to be respectively replaced, the block address being stored in the redundancy memory unit. Therefore, just one deactivation of that memory block of the memory blocks to be activated simultaneously which is to be replaced by the redundant row line is carried out via the corresponding deactivation line. Consequently, in the case of redundancy, all of the memory blocks of the block group are not deactivated.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory with interblock redundancy, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.